Memory control systems read from memory and write to memory. FIG. 1 illustrates a block diagram of a prior art configuration of a memory control system. A master 110 reads and writes to memory modules 150. The master 110 includes an input/output cell (IOC) 115. The IOC 115 permits the master 110 to interact with the IOCs 155a-155n of the memory modules 150a-150n, respectively. A memory channel 160 connects the IOC 115 of the master 110 with the IOCs 155a-155n of memory modules 150a-150n, respectively. The master 110 and memory modules 150a-150n on the memory channel 160 use a source synchronous scheme to send and receive data, in which common timing signals are used by the master 110 and memory modules 150a-150n for data transfer.
Memory access is made according to clock 180. The clock 180 provides a clock signal to each of the memory modules 150a-150n and to the master 110. This clock signal is the Clock-To-Master (CTM) signal 170. Furthermore, the master 110 returns a Clock-From-Master (CFM) signal 175. The CTM 170 and CFM 175 signals are short circuited together in the master 110. Thus, the CTM 170 and CFM 175 signals appear identical to the master 110.
The last memory module 150n is coupled to terminating resistors 195. The terminating resistors 195 prevent reflection of the transmission signals. The terminating resistors 195 are coupled between a termination voltage source V.sub.t 190 and the last memory module 150n. A termination resistor is further coupled to the CFM 175 signal, terminating the CFM 175 signal. Because of the high speed communication between the master 110 and the memory modules 150a-150n, every transmission line is terminated using a terminating resistor 195.
When the master 110 drives a data signal to write to one of the memory modules 150a-150n, the master 110 delivers a full swing signal on the memory channel 160. Upon arrival at the terminating resistors 195, the signal is fully terminated. When one of the memory modules 150a-150n drives a signal to the master 110, the signal is only pulled to half of its nominal voltage swing because the impedance seen by the memory module 150a-150n is half of the channel load impedance. When the signal reaches the master 110, the signal doubles in amplitude because of the open transmission line. Therefore, the master 110 can detect a full swing signal.
Adding a second master 230 that can also read from and write to memory into a memory control system is advantageous. However, placing a second master 230 into the above described system is difficult. The signal from the memory module 150a-150n is at half-strength until the signal is reflected by the open transmission line of the master 110. Thus, it is difficult to configure the second master 230 to read from memory.